chercheur en milieu académique*

Coordonnées

Doctorat

Intitulé : Sciences pour l'ingénieur : spécialité Micro et Nanoélectronique
1ère inscription en thèse : Octobre 2014
École doctorale : SCIENCES POUR L'INGENIEUR : Mécanique, Physique, Micro et Nanoélectronique
Date de soutenance de la thèse : 6 Décembre 2017
Sujet : mémoires 3D haute densité à base de technologies résistives: architecture et circuit
Directeur de thèse : Jean-Michel PORTAL
Co-directeur : Mathieu MOREAU
Unité de recherche : IM2NP - Institut Matériaux Microélectronique Nanosciences de Provence
Intitulé de l'équipe :

Master

Intitulé : Master recherche MINELEC
Septembre 2014 - Aix Marseille Université
Mention : Très bien

Langues vivantes

Français : C2 - Courant
Espagnol : A1 - Débutant
Anglais : C2 - Maternel

Production scientifique

  • SneakPath Compensation Circuit for Programming and Read Operations in RRAM-based CrossPoint Architectures
    2015 15th Non-Volatile Memory Technology Symposium (NVMTS) 2015
    A. Levisse; B. Giraud ; J. P. Noël ; M. Moreau ; J. M. Portal
  • Vertical CBRAM (V-CBRAM): From Experimental Data to Design Perspectives
    2016 IEEE 8th International Memory Workshop (IMW) 2016
    G. Piccolboni; M. Parise ; G. Molas ; A. Levisse ; J. M. Portal ; R. Coquand ; C. Carabasse ; M. Bernard ; A. Roule ; J. P. Noel ; B. Giraud ; M. Harrand ; C. Cagli ; T. Magis ; E. Vianello ; B. De Salvo ; G. Ghibaudo ; L. Perniola
  • Design Considerations During Programing Steps for bipolar OxRAM-Based Crosspoint Architecture
    LEADING EDGE EMBEDDED NON VOLATILE MEMORIES 2015 2015
    A. Levisse, B. Giraud, M. Moreau, J.M. Portal
  • Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures
    Nanoarch '16: IEEE/ACM International Symposium on Nanoscale Architectures Proceedings 2016
    A. LEVISSE, B. GIRAUD, J.P. NOËL, M. MOREAU, J.M. PORTAL
  • Architecture, Design and Technology Guidelines for Crosspoint Memories
    Nanoarch 20017 2017
    A. Levisse, P. Royer, B. Giraud, J.P. Noel, M. Moreau, J.M. Portal
  • Design and Simulation of a 128kb Embedded Non-Volatile Memory based on a Hybrid RRAM (HfO2) / 28nm FDSOI CMOS Technology
    IEEE Transactions on Nanotechnology (TNANO) 2017
    J.-M. Portal, M. Bocquet, S. Onkaraiah, M. Moreau, H. Aziza, D. Deleruyelle, K. Torki, E. Vianello, A. Levisse, B. Giraud, O. Thomas, F. Clermidy
  • Design Methodology for Area and Energy Efficient OxRAM-based Non-Volatile Flip-Flop
    IEEE International Symposium on Circuits and Systems (ISCAS) 2017
    M. Nataraj, A. Levisse, B. Giraud, J.-P. Noel, P. Meinerzhagen, J.M. Portal, P.-E. Gaillardon
  • Self-rectifying Behavior and Analog Switching Under Identical Pulses Using Tri-layer RRAM Crossbar Array for Neuromorphic Systems
    IEEE International Memory Workshop (IMW) 2017
    M. Alayan, E. Vianello, L. Larcher, A. Padovani, A. Levisse, N. Castellani, C. Charpin, S. Bernasconi, G. Molas, J.M. Portal, B. De Salvo, L. Perniola
  • High Density Emerging Resistive Memories: What are the Limits?
    IEEE Latin American Symposium on Circuits and Systems (LASCAS) 2017
    A. Levisse, B. Giraud, J.P. Noel, M. Moreau, J.M. Portal
  • New perspectives for multicore architectures using advanced technologies
    IEEE International Electron Devices Meeting (IEDM) 2016
    F. Clermidy, P. Vivet, D. Dutoit, Y. Thonnart, J.L. Gonzales, J.P Noël, B. Giraud, A. Levisse, O. Billoint, S. Thuriès
  • Functionality and reliability of resistive RAM (RRAM) for non-volatile memory applications
    VLSI Technology, Systems and Application (VLSI-TSA) 2016
    G. Molas, G. Piccolboni, M. Barci, B. Traore, J. Guy, G. Palma, E. Vianello, P. Blaise, J. M. Portal, M. Bocquet, A. Levisse, B. Giraud, J. P. Noel, M. Harrand, M. Bernard, A. Roule, B. De Salvo, L. Perniola
  • CBRAM corner analysis for robust design solutions
    Non-Volatile Memory Technology Symposium (NVMTS) 2014
    F. Longnos, M. Reyboz, N. Jovanovic, A. Levisse, T. Benoist, G. Suraci, O. Thomas, E. Vianello, G. Molas, B. De Salvo, L. Perniola
  • OxRAM-based Pulsed Latch for Non-Volatile Flip-Flop in 28nm FDSOI
    SOI-3D-Subthreshold Microelectronics Technology Unified Conference(S3S) 2014
    A. Levisse, N. Jovanović, E. Vianello, J.M. Portal, O. Thomas
  • Mémoire résistive unipolaire
    N/A 2016
    A.Levisse, B. Giraud, J-P. Noel
  • Method and circuit for controlling programming current in a non-volatile memory array
    N/A 2015
    A.Levisse
  • Advanced memory solutions for emerging circuits and systems
    IEEE International Electron Devices Meeting (IEDM) 2017
    B. Giraud; A. Makosiej; R. Boumchedda; N. Gupta; A. Levisse; E. Vianello; J.-P. Noel
  • In-depth investigation of programming and reading operations in RRAM cells integrated with Ovonic Threshold Switching (OTS) selectors
    IEEE International Electron Devices Meeting (IEDM) 2017
    M. Alayan; E. Vianello; G. Navarro; C. Carabasse; S. La Barbera; A. Verdy; N. Castellani; A. Levisse; G. Molas; L. Grenouillet; T. Magis; F. Aussenac; M. Bernard; B. DeSalvo; J. M. Portal; E. Nowak