Soutenance de thèse de Capucine LECAT--MATHIEU DE BOISSAC

Les travaux de la thèse auront pour objectif de répondre aux besoins grandissants de solutions techniques de hautes performances et répondant au niveau de robustesse requis par les applications spatiales ou automobiles. Ces travaux auront ainsi pour contexte l'utilisation de nœuds technologiques inférieurs à 40 nm, principalement de type FD-SOI, ainsi que l'utilisation de systèmes sur puce à hautes performances et contraints en consommation, tels que ceux issus du marché de la téléphonie mobile. Il s'agira de déterminer l'efficacité des solutions de conception robustes usuelles lorsqu'elles sont appliquées à un nœud technologique avancé. Il s'agira également de déterminer, dans un système sur puce tel qu'évoqué précédemment, les différentes sources de défaillances possibles, et l'impact des caractéristiques de ces systèmes sur ces défaillances, à savoir le fonctionnement à haute fréquence et à consommation énergétique réduite, notamment en raison de l'utilisation d'une tension d'alimentation plus faible. Les travaux devront prendre en considération les principaux effets des impacts de particules ionisantes, tels que le SEU, le SET, et le TID, et veiller à ce que les solutions permettant d'obtenir ce niveau de tolérance requis soient compatibles avec les contraintes de performances initiales. Cela implique également la capacité à mesurer ces effets, à comprendre leur impact sur les éléments qui composent le système et à utiliser ces informations pour appliquer de nouvelles solutions de robustesse et vérifier leur efficacité avant fabrication. Les travaux devront s'appuyer sur les études récentes et les premières réalisations publiées dans la littérature, qui démontrent le champ d'innovation possible offert par le sujet. En parallèle de l'étude bibliographique, les travaux de thèse débuteront par la décomposition des différents éléments qui constituent le SoC, en se focalisant sur les dispositifs numériques tels que les cellules séquentielles, les mémoires, ou les unités logiques (microcontrôleur, processeur). Suivra l'étude de la sensibilité de ces éléments aux différents effets liées aux impacts de particules ionisantes, à la fois au niveau technologique et au niveau système, et la construction de la méthodologie adéquate pour y parvenir efficacement. Il s'agira ensuite de développer des structures de mesures des différents effets, afin d'être en mesure de proposer des solutions de conception robustes innovantes des différents éléments du système en respectant les contraintes en vitesse, et performance, et d'en mesurer le résultat.

Embedded systems utilized in harsh radiation environments are experiencing an unprecedented boom. New actors have accelerated the pace of putting new satellites into orbit, and the integrated equipment complexity is increasing. In order to offer communication services with wide coverage, low earth orbit satellite launching programs rely on satellite constellations. Other domains like the automotive industry are at the origin of this development: driven by the advent of so-called intelligent vehicles, capable of anticipating accidents by analysing the environment, with vehicle autonomy as a medium-term objective. The level of robustness of the circuits is therefore particularly high, given the consequences of a failure. To meet these new needs, the electronics must be disruptive. First, it relies on advanced technologies in order to achieve the necessary performance to accomplish the tasks. Among these technologies, Ultra-Thin Body and Box Fully Depleted SOI (UTBB FD-SOI), offer remarkable intrinsic radiation resistance as well as a wider range of backside biases allowing for greater performance modulation, static and/or dynamic transistors, as well as the use of longer gate lengths at no additional cost in area. Second, embedded systems have also evolved, moving from the full-custom approach to the use of components used in the mobile phone market. There is a growing interest in RISC-V core-based solutions, which offer a wide range of functions and show interesting performances in terms of operating speed and power consumption. However, the combined use of advanced technologies and Systems-On-a-Chip (SoCs) based on consumer market solutions to meet the needs of the automotive or space industry requires research on various aspects, especially as the occurrence of errors is boosted by the large number of satellites each incorporating a growing number of devices. The effects of a particle impact on a digital device are mainly soft errors, caused by SEUs and SETs, and the drift of parameters of the devices as a result of dose accumulation, namely Total Ionizing Dose (TID). Many solutions have been developed to harden sequential and memory elements, with several levels of resistance to SEUs. However, the viability of these solutions is challenged by their cost in terms of area and performance, as well as the reduction in the supply voltage of the circuits, imposed both by the power budget allocated to the system and the range of voltages supported by the advanced technologies, which considerably increases sensitivity to radiation. There are few technical solutions allowing to counter the effects linked to the SETs and to the TID. The aim of the thesis was to meet the growing needs for high performance technical solutions that meet the level of robustness required by space or automotive applications. The context of this work was the use of technological nodes of less than 40 nm, mainly of the FD-SOI type, as well as the use of high-performance systems on a chip and constrained in consumption, such as those from the mobile telephony market. A first approach of this project was to study the influence of operating parameters such as supply voltage and back-gate biasing on Single-Event Transients (SETs); an integrated test structure for particle-induced glitches detection was designed in several technologies, and tested under various cocktails of particle types. This work, complemented with modeling studies, allowed to evaluate quantitatively the impact of technological parameters, as well as typical low-power levers on logic cells sensitivity. On a higher level of abstraction, one objective was the determination of the various sources of possible failures in SoCs, and the impact of the operating context on such failures. Based on the previous studies and designs, the ultimate objective was to develop a low-power, safety-aware System-on-Chip with real-time SER assessment and dynamic SER compensation.